Quantum Error Correction Engineer (Hardware-Aware)

About the Role

We are building a system that implements surface-code quantum error correction with a hardware-accelerated pipeline (multi-FPGA). This role is for a surface-code implementation specialist who understands the surface code deeply and has practical experience with decoder implementations and syndrome-processing pipelines. You will translate algorithmic choices into concrete dataflows, executable reference models, and unambiguous specs for our FPGA team.

Responsibilities

• Own the surface-code implementation plan (algorithm → implementation).
• Define the full syndrome processing and decoding workflow for the chosen surface-code setup.
• Identify performance targets: cycle-level latency constraints, throughput requirements, and scaling behavior.
• Define decoder strategy and practical implementation details suitable for real-time/streaming constraints.
• Provide implementation-ready descriptions: data structures, update rules, scheduling, and acceptable approximations.
• Collaborate with the FPGA architect to partition functionality between FPGA and host/control software.
• Create detailed implementation artifacts for FPGA execution: state machines, message formats, boundary conditions, and corner cases.
• Deliver reference implementations in Python/C++ (or similar) to generate expected outputs and test vectors.
• Provide golden models and test vectors for verification, including explicit fault/noise model assumptions.
• Support integration and validation: debug mismatches between reference models and hardware, and define success metrics (logical error rate targets, latency budget, resource scaling).

Qualifications

Must-have qualifications (non-negotiable)

• Deep working knowledge of surface code QEC beyond textbook level (stabilizers, syndrome extraction, decoding, boundaries/defects or lattice surgery).
• Hands-on implementation experience with at least one of: surface-code decoder implementation (research prototype or product); real-time syndrome processing pipeline; or hardware-aware acceleration (FPGA/GPU/ASIC) for decoding or related graph problems.
• Strong engineering skills in Python and/or C++ for reference models, test generation, and performance experiments.
• Ability to write precise, unambiguous implementation specs that a hardware team can execute.

Nice-to-have (strong plus)

• Familiarity with practical decoder families (examples: MWPM-style, union-find, belief propagation / weighted BP, or other practical variants).
• Comfort with hardware constraints: streaming dataflows, fixed-point reasoning, memory locality, and pipeline scheduling.
• Prior collaboration with FPGA/ASIC teams, including verification and bring-up realities.
• Open-source contributions, publications, or prior work demonstrating surface-code implementation.

What success looks like

• A clear decoder/workflow choice with documented tradeoffs.
• A validated reference model and test harness that produce golden outputs.
• A complete implementation map for FPGA: inputs/outputs, message formats, timing assumptions, and corner cases.
• Smooth integration with our multi-FPGA system and measurable performance progress against defined metrics.

How to apply

• Send to rdumke@aqsolotl.com: Resume/LinkedIn profile; a short description of your most relevant surface code implementation work; links to any code, papers, talks, or projects (optional but highly valuable).